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w39l040 512k 8 cmos flash memory publication release date: february 10, 2003 - 1 - revision a3 1. general description the w39l040 is a 4mbit, 3.3-volt only cmos flash memory organized as 512k 8 bits. for flexible erase capability, the 4mbits of data are divided in to 8 uniform sectors of 64 kbytes, which are composed of 16 smaller even pages with 4 kbytes. the byte-wide ( 8) data appears on dq7 ? dq0. the device can be programmed and erased in-system with a standard 3.3v power supply. a 12-volt v pp is not required. the unique cell architecture of the w39l040 results in fast program/erase operations with extremely low current consumpti on (compared to other comparable 3.3-volt flash memory products). the device can also be programmed and erased by using standard eprom programmers. 2. features ? single 3.3-volt operations ? 3.3-volt read ? 3.3-volt erase ? 3.3-volt program ? fast program operation: ? byte-by-byte programming: 50 s (max.) ? fast erase operation: ? chip erase cycle time: 100 ms (max.) ? sector erase cycle time: 25 ms (max.) ? page erase cycle time: 25 ms (max.) ? read access time: 70/90 ns ? 8 even sectors with 64k bytes each, which is composed of 16 flexible pages with 4k bytes ? any individual sector or page can be erased ? hardware protection: ? optional 16k byte or 64k byte top/bottom boot block with lockout protection ? flexible 4k-page size can be used as parameter blocks ? typical program/erase cycles: 1k/10k ? twenty-year data retention ? low power consumption ? active current: 10 ma (typ.) ? standby current: 2 a (typ.) ? end of program detection ? software method: toggle bit/data polling ? ttl compatible i/o ? jedec standard byte-wide pinouts ? available packages: 32l plcc, 32l tsop (8 x 20 mm) and 32l stsop (8 x 14 mm)
w39l040 - 2 - 3. pin configurations 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 #oe a10 #ce dq7 a 1 2 a 1 6 v d d # w e a 1 5 a 1 7 32l plcc v s s a 1 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 dq0 dq1 dq2 v #oe a10 #ce dq7 dq6 dq5 dq4 dq3 32l tsop & stsop a15 a12 a7 a6 a5 a4 v #we a14 a13 a8 dd a11 a9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a17 ss a18 4. block diagram control output buffer decoder core array #ce #oe #we a0 . . a18 . . dq0 dq7 v dd v ss 5. pin description symbol pin name a0 ? a18 address inputs dq0 ? dq7 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply v ss ground
w39l040 publication release date: february 10, 2003 - 3 - revision a3 6. functional description device bus operation read mode the read operation of the w39l040 is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the chip is de-selected and only standby power will be consum ed. #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. write mode device erasure and programming are accomplished vi a the command register. the contents of the register serve as inputs to the in ternal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with t he address and data information needed to execute the command. the command register is written by bringing #we to logic low state, while #ce is at logic low state and #oe is at logic hi gh state. addresses are latched on the falling edge of #we or #ce, whichever happens later; while data is latched on the rising edge of #we or #ce, whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the er ase/programming waveforms for specific timing parameters. standby mode there are two ways to implement the standby m ode on the w39l040 device, both using the #ce pin. a cmos standby mode is achieved with the #ce input held at v dd 0.3v. under this condition the current is typically reduced to less than 15 a (max). a ttl standby mode is achieved with the #ce pin held at v ih . under this condition the current is typically reduced to 2 ma(max). in the standby mode the outputs are in the hi gh impedance state, independent of the #oe input. output disable mode with the #oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. auto-select mode the auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be progra mmed with its corresponding programming algorithm. this mode is functional over the ent ire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5v to 12.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by t oggling address a0 from v il to v ih . all addresses are don t cares except a0 and a1 (see "auto-select codes").
w39l040 - 4 - the manufacturer and device codes may also be r ead via the command register, for instance, when the w39l040 is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in "auto-select codes". byte 0 (a0 = v il ) represents the manufacturer s code (winbond = dah) and byte 1 (a0 = v ih ) the device identifier code (w39l040 = b6hex ). all identifiers for manufac turer and device will exhibit odd parity with dq7 defined as the parity bit. in order to read the proper device codes when executing the auto-select, a1 must be low state. data protection the w39l040 is designed to offer protection against acci dental erasure or programming caused by spurious system level signals that may exist dur ing power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents onl y occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v dd power-up and power-down transitions or system noise. boot block operation there are four alternatives to set the boot blo ck. either 16k-byte or 64k -byte in the top/bottom location of this device can be locked as boot blo ck, which can be used to store boot codes. it is located in the last 16k/64k byte s or first 16k/64k bytes of the memory with the address range from 7c000/ 70000(hex) to 7ffff(hex) for top locati on or 00000(hex) to 03fff/0ffff(hex) for bottom location. see command codes for boot block lockout enable for t he specific code. once this feature is set the data for the designated block cannot be erased or pr ogrammed (programming lockout), other memory locations can be changed by the regular programming method. in order to detect whether the boot block feature is set on the first/last 16k/64k-bytes block or not, users can perform software command sequence: enter the product identification mode (see command codes for identification/ boot block lockout detection for specific code), and then read from address 0002(hex) for first (bottom) location or 7fff2(hex) for last (top) location. if the dq0/dq1 of output data is "0/1," the 16k-b ytes boot block programming lockout feature will be activated; if the dq0/dq1 of output data is "1/1," the 64k-bytes boot block programming lockout feature will be activated. if the dq0/dq1 of output data is "0/0," for both 16k/64k-bytes boot block, the lockout feature will be inactivated and the block can be erased/programmed. to return to normal operation, perform a three- byte command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot blo ck lockout detection. low v dd inhibit to avoid initiation of a write cycle during v dd power-up and power-down, the w39l040 locks out when v dd < 2.0v (see dc characteristics section fo r voltages). the write and read operations are inhibited when v dd is less than 2.0v typical. the w39l040 ignores all write and read operations until v dd > 2,0v. the user must ensure that the control pins are in the correct logic state when v dd > 2.0v to prevent unintentional writes. write pulse "glitch" protection noise pulses of less than 10 ns (typical) on #oe, #ce, or #we will not initiate a write cycle.
w39l040 publication release date: february 10, 2003 - 5 - revision a3 logical inhibit writing is inhibited by holding any one of #oe = v il , #ce = v ih , or #we = v ih . to initiate a write cycle #ce and #we must be a logical zero while #oe is a logical one. power-up write and read inhibit power-up of the device with #we = #ce = v il and #oe = v ih will not accept commands on the rising edge of #we except 5ms delay (see the power up timi ng in ac characteristics). the internal state machine is automatically reset to the read mode on power-up. command definitions device operations are selected by writing s pecific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "command definitions " defines the valid register command sequences. read command the device will automatically power-up in the read state. in this case, a command sequence is not required to read data. standard microprocessor read cycl es will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. the device will automatically returns to r ead state after completing an embedded program or embedded erase algorithm. refer to the ac read characteristics and wave forms for the specific timing parameters. auto-select command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be acce ssible while the device resides in the target system. prom programmers typically access the si gnature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desirable system design practice. the device contains an auto-select command operat ion to supplement traditional prom programming methodology. the operation is initiated by writ ing the auto-select command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of dah. a read cycle from address xx01h returns the device code (w39l040 = b6hex). to terminate the operation, it is necessary to write the auto-select exit command sequence into the register. byte program command the device is programmed on a byte-by-byte basis. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. the program address and data are wr itten next, which in turn initiate the embedded program algorithm. addresses are latched on t he falling edge of #ce or #we, whichever happens later and the data is latched on the rising edge of #ce or #we, whichever happens first. the rising edge of #ce or #we (whichever happens first) begins programming using the embedded program
w39l040 - 6 - algorithm. upon executing the algorit hm, the system is not required to provide further controls or timings. the device will automatically provide adequat e internally generated program pulses and verify the programmed cell margin. the automatic programming operation is comple ted when the data on dq7 (also used as data polling) is equivalent to the data written to this bi t at which time the device returns to the read mode and addresses are no longer latched (see "hardwar e sequence flags"). therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during t he embedded program algorithm will be ignored. if a hardware reset occurs during the programming operati on, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data "0" cannot be programmed back to a "1". attempting to program 0 back to 1, the toggle bit will stop toggling. only erase operations can convert "0"s to "1"s. refer to the programming command flow chart us ing typical command strings and bus operations. chip erase command chip erase is a six-bus-cycle operation. there are two "unlock" write cycles , followed by writing the "set-up" command. two more "unl ock" write cycles are asserted, followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devic e will automatically erase and verify the entire memory for an all one data pattern. the eras e is performed sequentially on each sectors at the same time (see "feature"). the syst em is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last #we pulse in the command sequence and terminates when the data on dq7 is "1" at whic h time the device returns to read the mode. refer to the erase command flow chart usi ng typical command strings and bus operations. sector/page erase command sector/page erase is a six bus cycles operation. t here are two "unlock" write cycles, followed by writing the "set-up" command. two more "unlock" write cycles t hen follows by the sector erase command. the sector/page address (any address loca tion within the desired sector/page) is latched on the falling edge of #we, while the command (30h /50h) is latched on the rising edge of #we. sector/page erase does not require the user to pr ogram the device prior to erase. when erasing a sector/page or sectors/pages the remaining unselect ed sectors/pages are not a ffected. the system is not required to provide any controls or timings during these operations. the automatic sector/page erase begins after the er ase command is completed, right from the rising edge of the #we pulse for the last sector/page erase command pulse and terminates when the data on dq7, data polling, is "1" at which time the dev ice returns to the read mode. data polling must be performed at an address within any of the sectors/pages being erased. refer to the erase command flow chart usi ng typical command strings and bus operations.
w39l040 publication release date: february 10, 2003 - 7 - revision a3 write operation status dq7: data polling the w39l040 device features data polling as a me thod to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completi on of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a "0" at the dq7 output. upon completion of the embedded erase algorit hm, an attempt to read the device will produce a "1" at the dq7 output. for chip erase, the data polling is valid after t he rising edge of the sixth pulse in the six #we write pulse sequences. for sector erase, the data polling is valid after the last rising edge of the sector erase #we pulse. data polling must be performed at sector addresses within any of the sectors being erased. otherwise, the status may not be valid. just prior to the completion of embedded algor ithm operations dq7 may change asynchronously while the output enable (#oe) is asserted low. this m eans that the device is dr iving status information on dq7 at one instant of time and then that byte s valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq 7 has a valid data, the data outputs on dq0 ? dq6 may be still invalid. the valid data on dq0 ? dq7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase ti me-out (see "command definitions"). dq6: toggle bit the w39l040 also features the "toggle bit" as a me thod to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (#oe toggling) data from the device at any address will result in dq6 toggling between one and zero. once the embedded program or erase algorithm cycle is comp leted, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth #we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth #we pulse in the six write pulse sequence. for sector/page erase, the toggle bit is valid after the last rising edge of the sector/page erase #we pulse. the toggle bit is active during the sector/page erase time-out. either #ce or #oe toggling will cause dq6 to toggle.
w39l040 - 8 - table of operating modes device bus operations (v id = 12 0.5v) pin mode #ce #oe #we a0 a1 a9 dq0 ? dq7 read v il v il v ih a0 a1 a9 dout write v il v ih v il a0 a1 a9 din standby v ih x x x x x high z x v il x x x x high z/ dout write inhibit x x v ih x x x high z/ dout output disable v il v ih v ih x x x high z auto select manufacturers id v il v il v ih v il v il v id code auto select device id v il v il v ih v ih v il v id code auto-select codes (high voltage method) (v id = 12 0.5v) description #ce #oe #we a9 the other address dq[7:0] manufacturer id: winbond v il v il v ih v id all add = v il dahex device id: w39l040 v il v il v ih v id a1 = v ih , all other = v il b6hex sector address table sector a18 a17 a16 sector size (kbytes) address sa0 0 0 0 64 00000h ? 0ffffh sa1 0 0 1 64 10000h ? 1ffffh sa2 0 1 0 64 20000h ? 2ffffh sa3 0 1 1 64 30000h ? 3ffffh sa4 1 0 0 64 40000h ? 4ffffh sa5 1 0 1 64 50000h ? 5ffffh sa6 1 1 0 64 60000h ? 6ffffh sa7 1 1 1 64 70000h ? 7ffffh note: all sectors are 64k bytes in size.
w39l040 publication release date: february 10, 2003 - 9 - revision a3 command definitions command no. of 1st cycle 2nd cycle 3rd cycle 4th cy cle 5th cycle 6th cycle 7th cycle description cycles addr. (1) data addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3) 30 page erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 pa (4) 50 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in top boot block lockout ? 64k/16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40/70 7ffff xx (5) bottom boot block lockout - 64k/16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40/70 00000 xx (5) product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 notes 1. address format: a14 ? a0 (hex); data format: dq7 ? dq0 (hex) 2. either one of the two product id exit commands can be used. 3. sa: sector address sa = 7xxxxh for unique sector7 sa = 6xxxxh for unique sector6 sa = 5xxxxh for unique sector5 sa = 4xxxxh for unique sector4 sa = 3xxxxh for unique sector3 sa = 2xxxxh for unique sector2 sa = 1xxxxh for unique sector1 sa = 0xxxxh for unique sector0 4. pa: page address pa = 7fxxxh for page 15 in sector7 pa = 7exxxh for page 14 in sector7 pa = 6fxxxh to 60xxx for page 15 to page 0 in sector6 (please reference to left column) pa = 7dxxxh for page 13 in sector7 pa = 7cxxxh for page 12 in sector7 pa = 5fxxxh to 50xxx for page 15 to page 0 in sector5 (please reference to left column) pa = 7bxxxh for page 11 in sector7 pa = 7axxxh for page 10 in sector7 pa = 4fxxxh to 40xxx for page 15 to page 0 in sector4 (please reference to left column) pa = 79xxxh for page 9 in sector7 pa = 78xxxh for page 8 in sector7 pa = 3fxxxh to 30xxx for page 15 to page 0 in sector3 (please reference to left column) pa = 77xxxh for page 7 in sector7 pa = 76xxxh for page 6 in sector7 pa = 2fxxxh to 20xxx for page 15 to page 0 in sector2 (please reference to left column) pa = 75xxxh for page 5 in sector7 pa = 74xxxh for page 4 in sector7 pa = 1fxxxh to 10xxx for page 15 to page 0 in sector1 (please reference to left column) pa = 73xxxh for page 3 in sector7 pa = 72xxxh for page 2 in sector7 pa = 0fxxxh to 00xxx for page 15 to page 0 in sector0 (please reference to left column) pa = 71xxxh for page 1 in sector7 pa = 70xxxh for page 0 in sector7 5. xx: don't care
w39l040 - 10 - embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
w39l040 publication release date: february 10, 2003 - 11 - revision a3 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h page address/50h individual page erase (address/command): individual sector erase command sequence command sequence pause t ec /t sec /t pec
w39l040 - 12 - embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = any of the device addresses being erased during chip erase operation = any of the page addresses within the page being erased during page erase operation embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no pass
w39l040 publication release date: february 10, 2003 - 13 - revision a3 boot block lockout enable flow chart boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40/70 to address 5555 pause 2 ms exit 40 to lock 64k boot block 70 to lcok 16k boot block load data xx to address 7ffff/0 7ffff(xx) to lock top boot block 000000(xx) to lock bottom boot block
w39l040 - 14 - software product identification and boot block lockout detection flow chart product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout dt ti mode (3) read address = 0000 data = da read address = 0001 read address=02/7fff2 for bottom/top data:in dq0="1" or "0" for 64k boot block or dq1="1" or "0" for 16k boot block (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5 ) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s data = b6
w39l040 publication release date: february 10, 2003 - 15 - revision a3 7. dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential -2.0 to +4.6 v 0 to +70 c operating temperature -40 to +85 c storage temperature -65 to +125 c voltage on any pin to ground potential except a9 -2.0 to +4.6 v voltage on a9 pin to ground potential -2.0 to +13.0 v note: exposure to conditions beyond those lis ted under absolute maximum ratings may adversely affect the life and reliability of the device. dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c or -40 to 85 c) limits parameter sym. test conditions min. typ. max. unit power supply current i dd #ce = #oe = v il , #we = v ih , all dqs open, address inputs = v il /v ih , at f = 5 mhz - 10 20 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all dqs open other inputs = v il /v ih - 1 2 ma standby v dd current (cmos input) i sb 2 #ce = v dd -0.3v, all dqs open other inputs = v dd -0.3v/ v ss - 2 15 a input leakage current i li v in = v ss to v dd - - 1 a output leakage current i lo v out = v ss to v dd - - 1 a input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.4 ma 2.4 - - v pin capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions typ. max. unit input capacitance c in v in = 0v 6 8 pf output capacitance c out v out = 0v 10 12 pf
w39l040 - 16 - 8. ac characteristics ac test conditions parameter conditions input pulse levels 0v to 3v input rise/fall time <5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf ac test load and waveform +3.3v 1.2k 2.1k d out ? ? 30 pf (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output
w39l040 publication release date: february 10, 2003 - 17 - revision a3 ac characteristics, continued read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c or -40 to 85 c) w39l040-70 w39l040-90 parameter sym. min. max. min. max. unit read cycle time t rc 70 - 90 - ns chip enable access time t ce - 70 - 90 ns address access time t aa - 70 - 90 ns output enable access time t oe - 35 - 45 ns #ce low to active output t clz 0 - 0 - ns #oe low to active output t olz 0 - 0 - ns #ce high to high-z output t chz - 25 - 25 ns #oe high to high-z output t ohz - 25 - 25 ns output hold from address change t oh 0 - 0 - ns write cycle timing parameters parameter sym. min. typ. max. unit address setup time t as 0 - - ns address hold time t ah 40 - - ns #we and #ce setup time t cs 0 - - ns #we and #ce hold time t ch 0 - - ns #oe high setup time t oes 0 - - ns #oe high hold time t oeh 0 - - ns #ce pulse width t cp 100 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 40 - - ns data hold time t dh 10 - - ns byte programming time t bp - 35 50 s chip erase cycle time t ec - 50 100 ms sector/page erase cycle time t ep - 12.5 25 ms note: all ac timing signals observe the following guidelines for determini ng setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w39l040 - 18 - ac characteristics, continued power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms data polling and toggle bit timing parameters w39l040-70 w39l040-90 parameter sym. min. max. min. max. unit #oe to data polling output delay t oep - 35 - 45 ns #ce to data polling output delay t cep - 70 - 90 ns #oe to toggle bit output delay t oet - 35 - 45 ns #ce to toggle bit output delay t cet - 70 - 90 ns
w39l040 publication release date: february 10, 2003 - 19 - revision a3 9. timing waveforms read cycle timing diagram address a18-0 dq7-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z #we controlled command write cycle timing diagram address a18-0 dq7-0 data valid t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh #ce #oe #we
w39l040 - 20 - timing waveforms, continued #ce controlled command write cycle timing diagram high z data valid dq7-0 t as t ah t cph t oeh t dh t ds t cp t oes address a18-0 #ce #oe #we chip erase timing diagram sb2 sb1 sb0 address a18-0 dq7-0 sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 #ce #oe #we
w39l040 publication release date: february 10, 2003 - 21 - revision a3 timing waveforms, continued sector/page erase timing diagram sb2 sb1 sb0 address a18-0 dq7-0 sb3 sb4 sb5 internal erase starts six-byte commands for 3.3v-only sector/page erase t wp t wph t ep 5555 2aaa 5555 5555 2aaa sa/pa aa 55 80 aa 55 30/50 sa = sector address, pa = page address please refer to page 9 for detail information #ce #oe #we #data polling timing diagram address a18-0 dq7 x x x x t cep t oeh t oep t oes t ec t bp or an an an an #ce #oe #we
w39l040 - 22 - timing waveforms, continued toggle bit timing diagram address a18-0 dq6 t oeh t oes t bp or t ec #ce #oe #we
w39l040 publication release date: february 10, 2003 - 23 - revision a3 10. ordering information part no. access time (ns) power supply current max. (ma) standby v dd current max. (ma) package operating temp. ( c) cycle w39l040p-70 70 20 2 32l plcc 0 ? 70 1k w39l040p-90 90 20 2 32l plcc 0 ? 70 1k w39l040t-70 70 20 2 32l tsop (8 x 20 mm) 0 ? 70 1k w39l040t-90 90 20 2 32l tsop (8 x 20 mm) 0 ? 70 1k w39l040q-70 70 20 2 32l stsop (8 x 14 mm) 0 ? 70 1k w39l040q-90 90 20 2 32l stsop (8 x 14 mm) 0 ? 70 1k w39l040p-70b 70 20 2 32l plcc 0 ? 70 10k w39l040p-90b 90 20 2 32l plcc 0 ? 70 10k W39L040T-70B 70 20 2 32l tsop (8 x 20 mm) 0 ? 70 10k w39l040t-90b 90 20 2 32l tsop (8 x 20 mm) 0 ? 70 10k w39l040q-70b 70 20 2 32l stsop (8 x 14 mm) 0 ? 70 10k w39l040q-90b 90 20 2 32l stsop (8 x 14 mm) 0 ? 70 10k w39l040p-70j 70 20 2 32l plcc -40 ? 85 1k w39l040p-90j 90 20 2 32l plcc -40 ? 85 1k w39l040t-70j 70 20 2 32l tsop (8 x 20 mm) -40 ? 85 1k w39l040t-90j 90 20 2 32l tsop (8 x 20 mm) -40 ? 85 1k w39l040q-70j 70 20 2 32l stsop (8 x 14 mm) -40 ? 85 1k w39l040q-90j 90 20 2 32l stsop (8 x 14 mm) -40 ? 85 1k w39l040p-70k 70 20 2 32l plcc -40 ? 85 10k w39l040p-90k 90 20 2 32l plcc -40 ? 85 10k w39l040t-70k 70 20 2 32l tsop (8 x 20 mm) -40 ? 85 10k w39l040t-90k 90 20 2 32l tsop (8 x 20 mm) -40 ? 85 10k w39l040q-70k 70 20 2 32l stsop (8 x 14 mm) -40 ? 85 10k w39l040q-90k 90 20 2 32l stsop (8 x 14 mm) -40 ? 85 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w39l040 - 24 - 11. how to read the top marking example: the top marking of 32-pin tsop w39l040t-70 1 st line: winbond logo 2 nd line: the part number: w39l040t-70 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in '01, week 49 o: assembly house id: a means ase, o means ose, ... etc. b: ic revision; a means version a, b means version b, ... etc. sa: process code w39l040t-70 2138977a-a12 149obsa
w39l040 publication release date: february 10, 2003 - 25 - revision a3 12. package dimensions 32l plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 32l tsop (8 x 20 mm) a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
w39l040 - 26 - package dimensions, continued 32l stsop (8 x 14 mm) a a a 2 1 l l 1 y e h d d c min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm b e
w39l040 publication release date: february 10, 2003 - 27 - revision a3 13. version history version date page description a1 april 16, 2002 - initial issued a2 august 13, 2002 11 correct block erase as sector erase in the embedded erase algorithm 12 correct embedded #data polling algorithm a3 february 10, 2003 1, 3, 15 modify the standby current (cmos input) from 15 a to 2 a (typ.) and 50 a to 15 a (max.) headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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